1. Field of Invention
This invention relates to semiconductor devices fabrication on silicon on insulator (SOI) substrates and to layout methods for such semiconductor devices.
2. Description of Related Art
Plasma etching, sputtering, plasma chemical vapor deposition (i.e., plasma CVD), ion implantation and other plasma processes are widely employed in fabrication of semiconductor devices.
During the plasma process, the surface of the semiconductor substrate is irradiated with charged particles (i.e., ions an electrons) in the plasma. When the semiconductor substrate has a metal wire on its surface, which is not connected to the substrate, electric charges enter and accumulate in the metal wire. In other words, a wire on the surface of the substrate acts as an antenna to collect charges from the plasma.
Such accumulated charges induce charging-up and cause damage to the devices. For example, if a gate electrode of a metal-oxide-semiconductor (MOS) device (MOS transistor) is connected to the metal wire, a gate insulating film below the gate electrode may be damaged. That is, a high voltage due to the charging up is applied to the gate insulating film and thereby degrades the quality of the semiconductor device and, further, causes dielectric breakdown.
Because the amount of accumulated charge increases in proportion to the area of the wire, the voltage applied to the gate insulating film also increases in proportion to the ratio of the area of the wire to the area of the gate insulating film. Therefore, when the ratio of the area of the wire to the area of the gate insulating film, or an “antenna ratio”, exceeds a certain threshold value, the gate insulating film will be damaged.
Therefore, in the layout of semiconductor devices including MOS transistors, it is proposed to limit the antenna ratio between the area of the wire and that of the gate insulating film to be less than a predetermined value so that the gate insulating film is not damaged during a plasma process. For example, Japanese Unexamined Patent Publications Hei 8-97416 (U.S. Pat. No. 5,744,838), Hei 11-186394, and Hei 11-297836 (U.S. Pat. No. 6,421,816) disclose such method.
On the other hand, silicon on insulator (SOI) devices, in which MOS transistors are fabricated in an active layer on an insulating substrate, have been increasingly used in recent years. However, detailed investigation of an influence of the plasma process to the SOI device has not been reported.